1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of storing multi values.
2. Description of the Background Art
Among nonvolatile semiconductor memory devices, attention is being paid to an NROM (Nitride Read Only Memory) type flash EEPROM (hereinafter, referred to as NROM) as a kind of a flash EEPROM. An NROM is disclosed in U.S. Pat. Nos. 6,011,725 and 5,768,192.
FIG. 29 is a cross sectional view of a conventional flash EEPROM.
Referring to FIG. 29, a flash EEPROM includes a semiconductor substrate 1, a drain region 2, a source region 3, a floating gate 4, an insulating film 5, and a control gate 6.
Drain region 2 and source region 3 are formed with a predetermined interval in the main surface of semiconductor substrate 1. Floating gate 4 is formed on semiconductor substrate 1 between drain region 2 and source region 3. Control gate 6 is formed on floating gate 4. The surfaces of floating gate 4 and control gate 6 are covered with insulating film 5.
In the flash EEPROM, electrons are accumulated in floating gate 4. Therefore, floating gate 4 is covered with insulating film 5. Insulating film 5 prevents leakage of electrons from floating gate 4.
In the conventional flash EEPROM, it is difficult to thin insulating film 5. If insulating film 5 is thin, electrons are leaked from floating gate 4 and, as a result, data written in the flash EEPROM is easily dissipated. Therefore, it is limited to make the flash EEPROM finer.
FIG. 30 is a cross sectional view of a memory cell used for an NROM.
Referring to FIG. 30, the NROM includes semiconductor substrate 1, two diffusion bit lines 7A and 7B, oxide films 8 and 10, a nitride film 9, and a control gate 11.
Two diffusion bit lines 7A and 7B are formed with a predetermined interval in the main surface of semiconductor substrate 1. Oxide film 8 is formed on semiconductor substrate 1 between two diffusion bit lines. Nitride film 9 is formed on oxide film 8. Oxide film 10 is formed on nitride fi 9. Control gate 11 is formed on oxide film 10.
In the NROM, electrons can be accumulated in each of storing regions 9L and 9R in nitride film 9. That is, by accumulating electrons in physically different two positions in one cell, the NROM can store data of two bits per cell.
The electrons accumulated in storing regions 9L and 9R in nitride film 9 cannot freely move in nitride film 9 and remain in storing regions 9L and 9R for the reason that nitride film 9 is an insulating film.
The NROM is easily manufactured and the price is low. A memory cell array to which the NROM is applied has a configuration that diffusion bit lines and word lines cross perpendicular to each other. A diffusion bit line is shared by adjoining memory cells. Consequently, the area of the memory cell array can be reduced as compared with the conventional flash EEPROM.
An operation of writing data to the NROM is performed by injecting hot electrons to a channel. An operation of erasing data in the NROM is performed by injecting hot holes generated by tunneling between bands. In a reading mode, a current is passed in the direction opposite to that in a writing mode. The moving direction of electrons in the reading mode from storing region 9L is therefore the same as that in the writing mode to storing region 9R.
FIGS. 31A to 31D are diagrams showing the operations of writing/reading data to/from two storing regions 9L and 9R in an NROM type memory cell.
Referring to FIG. 31A, a memory cell MC is a memory cell of the NROM type. The gate of memory cell MC is connected to a word line WL. It is assumed that memory cell MC is connected to bit lines BL0 and BL1. Memory cell MC has storing region 9L on a bit line BL0 side and has, as shown in FIG. 31C, storing region 9R on bit line BL1 side.
First, the writing operation to storing region 9L will be described. Referring to FIG. 31A, in the case of writing data to storing region 9L, word line WL is activated. The potential of bit line BL0 is maintained at a write potential VCCW, and the potential of bit line BL1 is maintained at a ground potential GND. As a result, a write current Ifw flows from bit line BL0 to bit line BL1 via nonvolatile memory cell MC. At this time, data is written in storing region 9L.
Next, the operation of reading data from storing region 9L will be described. Referring to FIG. 31B, in the case of reading data of storing region 9L, word line WL is activated. The potential of bit line BL0 is maintained at ground potential GND, and the potential of bit line BL1 is maintained at a read potential VCCR. By detecting whether a read current Ifr flows from bit line BL1 to bit line BL0, data is read.
As described above, in storing region 9L, the current direction in the writing operation and that in the reading operation are opposite to each other.
The writing operation to storing region 9R will now be described. Referring to FIG. 31C, in the case of writing data to storing region 9R, word line WL is activated. The potential of bit line BL0 is maintained at ground potential GND, and the potential of bit line BL1 is maintained at write potential VCCW. As a result, write current Irw flows from bit line BL1 to bit line BL0. At this time, data is written in storing region 9R.
Next, the operation of reading data from storing region 9R will be described. Referring to FIG. 31D, in the case of reading data of storing region 9R, word line WL is activated. The potential of bit line BL0 is maintained at read potential VCCR and the potential of bit line BL1 is maintained at ground potential GND. By detecting whether a read current Irr flows from bit line BL0 to bit line BL1, data is read.
As described above, in the writing operation of the NROM, if a predetermined potential is applied to each of diffusion bit line and control gate, electrons can be accumulated in storing region 9L or 9R. However, if a potential is excessively applied in the writing operation, the following problems occur.
(1) There is the possibility that a threshold value of a memory cell becomes too high and data cannot be erased in a designated period in an erasing operation for the reason that if a potential is excessively applied at the time of a writing, excessive electrons are accumulated in nitride film 9. This problem can happen also in a conventional flash EEPROM.
(2) There is the possibility that data of two bits cannot be stored in each cell (hereinafter, referred to as two bits/cell). Specifically, in the NROM, it is necessary to accurately read storing region 9R irrespective of the state of storing region 9L and accurately read storing region 9L irrespective of the state of storing region 9R.
FIGS. 32A and 32B are diagrams for describing the reading operation of the NROM. FIGS. 32A and 32B show the case where electrons are accumulated in storing region 9L and electrons are not accumulated in storing region 9R.
FIG. 32A shows an NROM on which the writing operation is accurately performed, and FIG. 32B shows an NROM in which electrons are excessively accumulated in the writing operation.
Referring to FIG. 32A, in the case of reading data from storing region 9R, a predetermined potential is applied to diffusion bit line 7 and control gate 11. At this time, a depletion layer is expanded to a range V in semiconductor substrate 1. If the operation of writing data to storing region 9L is performed normally, the distribution of electrons stored-in storing region 9L lies within the range V. In this case, therefore, data of storing region 9R is read normally.
On the other hand, in the case of FIG. 32B, in the operation of reading data from storing region 9R, the depletion layer is expanded to the range V. However, a potential is excessively applied at the time of writing data to storing region 9L, the electron distribution expands to a range E. In the case of reading data from storing region 9R, due to the electron distribution exceeding the range V of the depletion layer, the threshold value increases. As a result, it may be erroneously recognized that storing region 9R is in a programmed state. This problem does not occur in a conventional flash EEPROM using the floating gate.
(3) There is the possibility that, in the writing operation, a part of electrons to be accumulated in storing regions 9L and 9R is accumulated in a position apart from each diffusion bit line.
FIG. 33 is a schematic diagram showing a state where a part of electrons is accumulated in a position apart from each diffusion bit line in the writing operation.
In FIG. 33, a part of electrons is stored in regions 12 and 13 apart from diffusion bit lines 7A and 7B, respectively.
In the case where electrons are stored in positions as shown in FIG. 33, even if a specific erase voltage is applied, all of the accumulated electrons cannot be erased. A region in which a strong electric field is generated when the erase voltage is applied is a portion in which the control gate and each diffusion bit line are adjacent to each other. The electrons accumulated in the adjacent portion are neutralized with holes injected at the time of erasing in the whole regions 9L and 9R. However, in the case where electrons are accumulated in positions such as regions 12 and 13 as shown in FIG. 33, a sufficient electric field is not applied to the regions in which a part of electrons are accumulated, so that holes for neutralizing electrons stored in the region are not sufficiently injected. As a result, the electrons in regions 12 and 13 are not neutralized as a whole. Therefore, the threshold value does not decrease after the erasing operation, so that resistance characteristic of the NROM deteriorates. This problem occurs due to a property peculiar to the NROM such that electrons cannot move in the electron accumulating layer at the time of programming. In a conventional flash EEPROM, as electrons and holes can freely move in the floating gate, such a problem cannot occur.
In order to solve the problems, it is necessary to suppress variations in the threshold value of a memory cell in the writing and erasing operations. That is, it is necessary to prevent application of an excessive write voltage at the time of a writing operation.